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Low temperature electron mobility and concentration under the gate of AlGaN/GaN field effect transistors 
Auteur(s): Sakowicz M., Tauk R., Lusakowski J., Tiberj A., Knap W., Bougrioua Z., Azize M., Lorenzini P., Karpierz K., Grynberg M.
(Article) Publié:
Journal Of Applied Physics, vol. 100 p.113726 (2006)
Ref HAL: hal-00543860_v1
DOI: 10.1063/1.2353786
WoS: 000242887400096
Exporter : BibTex | endNote
8 Citations
Résumé: High electron mobility field effect transistors were fabricated on AlGaN/GaN heterostructures and their magnetoresistance was measured at 4.2 K up to 10 T with simultaneous modulation of the gate potential. Low and high magnetic field data were used to determine the electron mobility (mu) and concentration (n), respectively, in the gated part of the transistor channel. With these measurements we present a method to determine mu and n under the gate of a transistor, which does not require knowledge of the transistor gate length, access resistance, threshold voltage, or capacitance. We discuss applications of this method for nanometer and ballistic transistors. (c) 2006 American Institute of Physics.
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Room temperature tunable detection of subterahertz radiation by plasma waves in nanometer ingaas transistors
Auteur(s): Teppe F., Orlov M., Fatimy A.E., Tiberj A., Knap W., Torres J., Gavrilenko V., Shchepetov A., Roelens Y., Bollaert S.
(Article) Publié:
Applied Physics Letters, vol. 89 p.222109.1-222109.3 (2006)
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Quantum and transport lifetimes of two-dimensional electrons gas in AlGaN/GaN heterostructures
Auteur(s): Lorenzini P., Bougrioua Z., Tiberj A., Tauk R., Azize M., Sakowicz M., Karpierz K., Knap W.
(Article) Publié:
Applied Physics Letters, vol. 87 p.232107 (2005)
Ref HAL: hal-00543864_v1
DOI: 10.1063/1.2140880
WoS: 000233723200045
Exporter : BibTex | endNote
16 Citations
Résumé: The transport and quantum lifetimes were respectively deduced from low-temperature mobility and Shubnikov-de Haas measurements as a function of carrier density in metal organic vapor phase epitaxy-grown AlGaN/GaN/sapphire heterostructures. We show experimentally that the lifetime ratio varies as a bell curve, qualitatively confirming a recent theoretical prediction. However the experimental ratio varied much less than was theoretically predicted: From 9 to 19 for carrier densities in 1-9x10(12) cm(-2) range. Moreover, we show the variation of quantum time with carrier density presents some discrepancy with the theoretical study. We also show that transport to quantum lifetime ratio cannot be used alone as a clear figure of merit from AlGaN/GaN heterojunctions. (c) 2005 Americian Institute of Physics.
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Strain effects in device processing of silicon-on-insulator materials
Auteur(s): Camassel J., Tiberj A.
Conférence invité: 11th International Conference on Solid Films and Surfaces (ICSFE-11) (MARSEILLE (FRANCE), FR, 2002-07-08)
Actes de conférence: APPLIED SURFACE SCIENCE, vol. 212 p.742-748 (2003)
Ref HAL: hal-00543872_v1
Exporter : BibTex | endNote
Résumé: Reporting on residual strain in silicon-on-insulator (SOI) materials we show that multi-insulating layer structures, in which silicon dioxide and silicon nitride are mixed with appropriate thicknesses, can lead to a new family of strain-free materials. This reduces only the original strain and, of course, does not significantly modify any process-induced effect. However, after proper annealing, this should help coming back to a better relaxation level. (C) 2003 Elsevier Science B.V. All rights reserved.
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Process-induced strain in silicon-on-insulator materials
Auteur(s): Tiberj A., Fraisse B., Blanc C., Contreras S., Camassel J.
Conference: Conference on Extended Defects in Semiconductors (EDS 2002) (BOLOGNA (ITALY), FR, 2002-06-01)
Ref HAL: hal-00543870_v1
Exporter : BibTex | endNote
Résumé: We present a detailed investigation of the influence of oxidation and thinning processes on the in-plane stress in silicon-on-insulator materials. Combining double x-ray diffraction, Fourier transformed infrared and micro-Raman spectroscopy, we show that one can separately evaluate the stress present in the silicon over layer, the buried oxide and the underlying (handle) silicon wafer at any time of a device-forming process.
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